1. Field of the Invention
The present invention relates generally to the art of semiconductor manufacturing and, more particularly, to a method of forming devices with dual oxide thicknesses.
2. Description of the Relevant Art
Semiconductor devices employ insulating layers to electrically isolate device, components such as conductive gates, from an underlying substrate. The insulating layers can be formed from an oxide material in general and silicon dioxide in particular. Forming an oxide layer is one of a number of processing steps in manufacturing devices wherein the oxide layer formation step generally includes placing a silicon wafer in a process tool, such as a furnace or rapid thermal annealer, and subjecting the silicon wafer to an ambient atmosphere containing oxygen at an elevated temperature. The oxygen reacts with the silicon surface of the wafer to form a thin oxide layer of generally uniform thickness. Thereafter, the wafer with thin oxide layer formed thereon, is subjected to further processing steps including, for example, the formation of one or more polysilicon gates.
Many modem programmable devices including EEPROMs are defined by sophisticated structures having dual oxide thicknesses. FIG. 1, for example, shows a cross-sectional view of an EEPROM having a multi-thickness oxide 12 along with a program transistor 14, a buried control gate 16, a floating gate 18, a sense transistor 20, and a read transistor 22. The multi-thickness oxide 12 includes a first or gate oxide 26 and a second or tunnel oxide 24. Proper operation of the EEPROM requires the tunnel oxide 24 to be significantly thinner when compared to the thickness of the gate oxide 26 for the following reasons.
The EEPROM shown in FIG. 1 can be "erased" or "programmed" by injection or removal of electrons onto floating gate 18. In the erase mode, a high voltage is connected to both the buried control gate 16 and gate 28 of program transistor 14. Concurrently, a low voltage (ground for example) is applied to source 30 of program transistor 14. Thus biased, a strong electric field is induced across tunnel oxide 24 between floating gate 18 and drain 32 of program transistor 14. This strong electric field induces electrons to tunnel from drain 32 to floating gate 18 causing an accumulation of negative charge thereon. Since floating gate 18 also acts as a gate to sense transistor 20, the accumulation of negative charge raises the threshold voltage of the associated sense transistor 20 which, in turn, inhibits current flow therethrough during a subsequent "read" mode.
In the program mode the control gate 16 and the source 30 of program transistor 14 are revered biased while program transistor is on thereby creating a strong reverse electric field across tunnel oxide 24. This reverse bias removes electrons from floating gate 18 by a tunneling mechanism. The removal of the electrons lowers the threshold voltage of sense transistor 20 which, in turn, promotes current flow therethrough during a subsequent "read" mode.
To achieve electron tunneling through tunnel oxide 24 in the presence of a strong electric field it is imperative that tunnel oxide 24 have a relatively thin cross-sectional thickness when compared to the thickness of gate oxide 26. Typically, a high quality EEPROM can be manufactured with tunnel oxide 24 having a thickness of 80-100 angstroms.
Prior art techniques for forming tunnel and gate oxides require multiple steps. The prior art technique will now be described with reference to FIGS. 2 through 9 which show a magnified view of region A in FIG. 1 after successive steps. More particularly, FIG. 2 shows silicon wafer 50 with a thin layer of oxide 26 formed thereon. The oxide is formed by reacting the silicon wafer 50 surface with an ambient atmosphere containing oxygen. This layer is used to form the gate oxide 26.
Thereafter, a layer of light sensitive photoresist 54 is deposited on the oxide 26 as shown in FIG. 3. The photoresist is selectively exposed to light transmitted through a photomask plate (not shown) having opaque and light transmissive areas. Light exposed regions of the photoresist are developed by subjecting the wafer to a washing technique which removes the exposed photoresist. FIG. 4 shows the result of the exposing and developing steps to create a window 56 through photoresist 54 to expose oxide 26.
The wafer is then subjected to an etching technique which removes oxide exposed by window 56 as shown in FIG. 5. This removal of the oxide provides an area on the silicon surface where tunnel oxide 24 can be grown. Before the tunnel oxide 24 can be formed, the photoresist material 54 must be removed because photoresist is formed of a carbon based material, and if the photoresist material is not removed prior to the tunnel oxide formation step, the photoresist will react in the high temperature oxygen environment needed to form the tunnel oxide, and inadvertently diffuse into the silicon window area which in turn precludes any formation of tunnel oxide thereon.
The photoresist removal technique, sometimes does not remove all of the photoresist material. It has been shown the removal technique may inadvertently leave behind bits and pieces of the photoresist on the surface of the silicon dioxide 52. FIG. 6 shows examples of residual photoresist particles remaining on the surface of silicon dioxide 52 after photoresist removal.
After removal of photoresist 54 the wafer is subjected to a second oxidation process to form the tunnel oxide on the exposed area. In this step like the step for forming the gate oxide, the wafer is subjected to an ambient of oxygen at elevated temperatures. However, oxygen diffuses through the gate oxide and reacts with the silicon thereunder thereby further growing the gate oxide. FIG. 7 shows the results of the formation of the tunnel oxide 24 and the further growth of gate oxide 26. However, as can be seen in FIG. 7 the resulting thickness of the gate oxide 26 is non-uniform due to the presence of the photoresist particles inadvertently remaining after photoresist removal. These particles inhibit further growth of the first oxide layer underneath the particles during formation of the tunnel oxide since oxygen penetratration is impeded by the photoresist and cannot react with the underlying surface of the silicon wafer.
FIGS. 8 and 9 show the results of depositing and selectively etching to form floating gate 18 and gate 28 of program transistor 14.
Several problems exist with EEPROMs having dual oxide thicknesses formed using the above described conventional techniques. These problems relate to manufacturability and reliability. With respect to manufacturability, the two oxidation steps needed to form the gate and tunnel oxides, increases the error deviation with respect to gate oxide thickness. The gate oxide is initially formed with a thickness less than what is ultimately required with the view of increasing the thickness during formation of the tunnel oxide. For example, in FIG. 2, the gate oxide thickness is grown with a thickness of, for example, 125 angstroms. The ultimate gate oxide thickness may be, for example, 150 angstroms. However, because the gate oxide also grows during the tunnel oxide formation step, it is necessary to initially make the gate oxide less than the required thickness. Because there are two separate oxidation steps which are implemented to form the gate oxide, there are two deviation errors associated therewith. In other words, there is a first error deviation associated with the growth of the initial 125 angstrom thick gate oxide and there is an additional standard deviation associated with the growth of the additional 25. These two standard deviations unduly increase the ultimate standard deviation associated with the gate oxide.
A further, more severe problem relates to device reliability. As can be seen in FIG. 9, gate 28 extends into gate oxide due to the gaps created step by the residual photoresist particles. In operation, gate 28 is subjected to high voltages during the "programming" and "erasing" of EEPROM 10. These voltages produce an electric field across gate oxide 26 which is directly proportional to the inverse of thickness of the underlying gate oxide. During the "programming" and "erasing " modes of EEPROM operation, gate oxide 26 is subjected to an unanticipated high electric field at areas of reduced thickness (i.e., the gaps created due to the residual photoresist). These high electric fields may cause the oxide to break down or rupture which in turn may render program transistor 14 inoperable.